LOW POWER SRAM DESIGN USING BLOCK PARTITIONING
نویسندگان
چکیده
منابع مشابه
Design of Low Power Sram Memory Using 8t Sram Cell
Low power design has become the major challenge of present chip designs as leakage power has been rising with scaling of technologies. As modern technology is spreading fast, it is very important to design low power, high performance, and fast responding SRAM (Static Random Access Memory) since they are critical component in high performance processors. The Conventional 6T SRAM cell is very muc...
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SRAM cell stability will be a primary concern for future technologies due to variability and decreasing power supply voltages. Advances in chip designing have made possible the design of chips at high integration and fast performance. Lowering power consumption and increasing noise margin have become two central topics in every state of SRAM designs.The Conventional 6T SRAM cell is very much pr...
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ژورنال
عنوان ژورنال: International Journal of Research in Engineering and Technology
سال: 2013
ISSN: 2321-7308,2319-1163
DOI: 10.15623/ijret.2013.0204003